Clock dividers can be implemented on most if not all FPGAs and they use very limited resources. While there is more than one way to do this, implementing a clock divider/scaler is the most popular and simplest option. It is easy to see that such large frequency square wave cannot be used for blinking an LED or generate clock/data signals for simpler interfaces such as UART/I2C/SPI where clocks run at a few KiloHertz. So it is important to generate a lower frequency clock/square wave for such purposes. For example, Numato Lab Mimas A7 has an onboard oscillator that runs at 100MHz. Usually, such clock available on these boards can be of very large frequency, which may not be suitable for some purposes. The oscillator generates a square wave (a.k.a clock signal) and feeds to the FPGA so that FPGA can use the clock to synchronize internal operations. In fact, most FPGA boards including Numato Lab Mimas A7 has a built-in oscillator that does exactly the same thing. Generating square wave is as simple as turning ON an IO, wait for x amount time, turn OFF the IO, wait for x amount of time and continue the cycle indefinitely. Square Wave (generated using numpy and scipy.

Simply put, a digital signal with exact same ON time and OFF time can be considered as a square wave. This is also known as the signal having a 50% duty cycle. The primary requirement is that the ON time (where the signal stays at HIGH state) and OFF time (where the signal stays at LOW state) are equal. A square wave is a signal that changes between HIGH state (Eg: 5V) and low state (Eg: 0V).

Mimas A7 Configuration downloader software (available at product page).

Mimas Artix 7 FPGA Development Board or a similar board.

Xilinx Vivado Design suite or Web pack (Download from Xilinx for free.

Although this article uses Numato Lab Mimas A7 for implementing and testing the code, the underlying theory and code should be applicable to any development board or FPGA currently available in the market. Since the concept is very simple, no vendor-specific IP needs to be used either. The code is written in Verilog but can be converted to VHDL with minimal effort. This article talks about how to generate a square wave using FPGA. Doing this exercise helps the learner get familiar with IOs, their configuration, and simple language constructs.

While learning FPGAs or embedded systems, generating a square wave is probably one of the simplest experiments to try out.

Period counter vhdl